// ----------------------------------------------------------------------------------------
// defines.v
// Global compile-time options for OTTO / PDP-8 simulation and hardware builds
// ----------------------------------------------------------------------------------------
//
// Notes:
// - These are Verilog preprocessor defines.
// - Enable only the options needed for the current build.
//
// - `default_nettype none` is intentionally kept at the end of this section
//   to catch undeclared or mistyped signals.
// ----------------------------------------------------------------------------------------



// ----------------------------------------------------------------------------------------
// Build target
// ----------------------------------------------------------------------------------------
//`SIMULATION` selects simulation-only features.
// Enable this when running under a Verilog simulator, such as Icarus Verilog.
// Leave it undefined for a real FPGA hardware build.
//`define SIMULATION


// ----------------------------------------------------------------------------------------
// Simulation debug options
// ----------------------------------------------------------------------------------------

// Trace instruction/microinstruction execution.
// Useful for debugging the CPU, but very verbose.
// Note that currently all these tracing lines are commented - edit them to use this flag
//`define trace_xec

// ----------------------------------------------------------------------------------------
// Memory extender debug
// ----------------------------------------------------------------------------------------
//`define trace_mext        // debug memory extender


// ----------------------------------------------------------------------------------------
// Initial machine state
// ----------------------------------------------------------------------------------------

// Initial program counter used by the simulation/front-panel startup logic.
// Most PDP-8 test programs and diagnostics are commonly started at 0200.
`define initial_PC      12'o0200

// Initial simulated Switch Register setting.
// Some DEC diagnostics expect SR = 7777 at startup.
/* For Adder Tests 11=LSB
SR00=1      SUPPRESS HALT ON ERROR
SR01=1      SUPPRESS ERROR TYPEOUT
SR02=1      LOOP ON ERROR
SR03=1      FAST TEST
SR04=0      LOOP IN CURRENT MEMORY BANK
SR05=1      RELOCATE TO NEXT EXISTING BANK
SR06-08     AMOUNT OF EXTENDED BANKS OF MEMORY
SR09=1      HALT AT END OF TEST
SR10=1      SUPPRESS END OF TEST TYPEOUT
SR11=1      LOOP ON PRESENT TEST 
`define swreg_setting   12'o0404        // for adder test
000 000 000 100*/

/* for memory extension test
//  SR00=1  // if 0 complete mem+time sharing, if 1 memory only
//  SR01=1  // end of test at 1565
//  SR02
//  SR09
//  SR09
//  SR09
//  SR09
//  SR09
//  SR09    // number of extension memory modules 
//  SR10    // field 0 not included
//  SR11
`define swreg_setting   12'o6001        // for mem ext
*/

`define swreg_setting   12'o0200

// note that the switch register is used for two purposes during simulation
// - on the very beginning of the ucode cicle it is interpreted as 'initial_PC
// - imediately after it becomes 'swreg_settings
// in a real machine, it should be real switches

// ----------------------------------------------------------------------------------------
// UART / Teletype simulation options
// ----------------------------------------------------------------------------------------

// Accelerate UART timing during simulation.
// Without this, simulated 9600 baud operation is very slow.
//`define sim_time

// Enable an internally emulated keyboard source for the UART/Teletype.
// Leave disabled when testing real UART loopback, such as Txd -> Rxd.
//`define emulated_keyboard

// Emulated keyboard timing defaults.
	// If FOCAL still reports an input-buffer related error (?11.18), increase EMUKBD_CHAR_DELAY

`ifndef EMUKBD_START_DELAY
`define EMUKBD_START_DELAY 32'd40000      // answer delay
`endif

`ifndef EMUKBD_CHAR_DELAY
`define EMUKBD_CHAR_DELAY 32'd5000        //inter-character delay
`endif


// ----------------------------------------------------------------------------------------
// RAM initialization
// ----------------------------------------------------------------------------------------

// Initialize RAM from a text file during simulation.
// The current blk_ram16kx12.v loader expects a file such as "default.mem"
// containing one octal address and one octal word per line:
//
//     0200 7300
//     0201 1206
//     ...
//
// Remember that this is simulation-only behavior.
//`define init_ram


// ----------------------------------------------------------------------------------------
// Toolchain notes
// ----------------------------------------------------------------------------------------

// XILINX_ISIM was automatically defined by the old Xilinx ISim environment.
// It should not be defined manually for Icarus Verilog.
// `define XILINX_ISIM


// ----------------------------------------------------------------------------------------
// Safety
// ----------------------------------------------------------------------------------------

// Make undeclared nets an error. This helps catch spelling mistakes.
`default_nettype none


// sorgente mux
`define	sPC   4'd0
`define	sMB   4'd1
`define	sMA   4'd2
`define	sAC   4'd3
`define	s00   4'd4
`define	sSR   4'd5
`define	sMO   4'd6 // MO = (MA)
`define	sEA   4'd7
`define	sIN   4'd8
`define	sMQ   4'd9
`define	sFLAGS 4'd10

// operazioni ALU: M SSSS CYin
// ALU operations
// bit 5 = mode 1=logic op, 0=arithmetic op
// bit 0 = CYF to ALU (significant only for ARITM ops)
`define	oTO     6'b111110	// LOGIC Y=A, CY=X 
`define	oAPLUS1 6'b000001	// ARITM Y=A, CY=1
`define	oAPLUSB 6'b010010	// ARITM Y=A+B, CY=0
`define	oAANDB  6'b110110	// LOGIC Y=A AND B, CY=0
`define	oZERO   6'b000111	// ARITM Y=-1, CY=1
`define	oCPL    6'b100000 // LOGIC Y=notA, CY=X
`define	o2CP    6'b001101 // ARITM Y=A-B-1, CY=1 (2's complement) ??? not used
`define	o7777   6'b000110 // ARITM Y-1, CY=0
`define	oAORB   6'b111100 // LOGIC Y=A OR B, CY=X

/* -------------------------------------------------------------------------
   2026-04-30 - MAJOR MODIFICATION: encoded REGLOAD destinations

   The original microinstruction destination field directly contained the
   active-low register load pattern. For example:

       `define dPC   8'b11111110
       `define dMA   8'b11111101
       `define dIR   8'b11111011
       `define dAC   8'b11100111   // two active bits
       `define dMB   8'b11011111
       `define dAB   8'b11011101   // MA and MB
       `define dSRA  8'b11101111   // shift right AC
       `define dSLA  8'b11110111   // shift left AC
       `define dMEM  8'b01111111   // write RAM
       `define dMQ   8'b10111111
       `define dXX   8'b11111111   // no destination

   This worked as long as all destinations fitted in the original 8-bit
   active-low pattern. The implementation of the missing PDP-8 processor IOT
   instructions required an additional destination/control condition, dFLAGS,
   used by the GTF/RTF-related logic.

   Since the microinstruction field could not be widened, the destination
   field is now encoded. The d... constants below are no longer active-low
   load patterns; they are compact numeric codes.

   REGLOADx, where "x" means "encoded", is read from the microinstruction.
   It is then decoded internally into the old active-low register-load format,
   with one extra bit:

       REGLOAD[7:0]  = original active-low load pattern
       REGLOAD[8]    = FLAGS control bit, active low

   This keeps most of the old datapath logic unchanged, while allowing the
   new FLAGS-related path to be selected when required. At present, the FLAGS
   bit is simply decoded here and tested in datapath.v.
   ------------------------------------------------------------------------- */

// Encoded ALU-bus destination / control codes.
// These are compact codes, not active-low load patterns.
`define dPC      8'd1
`define dMA      8'd2
`define dIR      8'd3
`define dAC      8'd4    // AC load; decoded pattern uses two active bits
`define dMB      8'd5
`define dAB      8'd6    // MA and MB
`define dSRA     8'd7    // shift right AC
`define dSLA     8'd8    // shift left AC
`define dMEM     8'd9    // write RAM
`define dMQ      8'd10
`define dFLAGS   8'd11   // FLAGS control path, used by processor IOTs
`define dPCMEM   8'd12   // replaces the old condition dPC & DMEM - with the new logic 
                         // values cannot be combined anymore
`define dXX      8'd15   // no destination


// selezione qualificatore microistruzioni
`define	qTRUE   5'd0 
`define	qFALSE  5'd1
`define	qDIRECT 5'd2
`define	qNOMEM  5'd3
`define	qCLA    5'd4
`define	qCLL    5'd5
`define	qMQA    5'd5
`define	qCMA    5'd6
`define	qCML    5'd7
`define	qMQL    5'd7
`define	qRAR    5'd8
`define	qRAL    5'd9
`define	qTWI    5'd10
`define	qIAC    5'd11
`define	qOFL    5'd12
`define	qGR2    5'd13
`define	qIOP    5'd14
`define	qRUN    5'd15
`define	qFREE   5'd16
`define	qSKP    5'd17
`define	qOSR    5'd18
`define	qHLT    5'd19
`define	qMB0    5'd20
`define	qAUTOI  5'd21
`define	qIRQ    5'd22
`define	qBSW    5'd23
`define	qGR3    5'd24
`define  qSWP    5'd25
`define	qGTF    5'd26
`define	qRTF    5'd27
`define	qCAF    5'd28
`define	qSKON   5'd29

// comandi RAM
`define	mRD 1'b1
`define	mWR 1'b0

// microopcodes
`define	uJPT  4'b0001 // salto condizionato dal qualificatore TRUE
`define	uJPF  4'b0101 // salto condizionato dal qualificatore FALSO
`define	uJPI  4'b0011 // salto attraverso tabella
`define	uCOND 4'b1000 // esecuzione condizionale della uIstr - se cond falsa diventa NOP
`define	uSTOP 4'b1111 // arresta simulazione

// operazioni sul LINK
`define	lkNOP 3'b000 // unchanged
`define	lkCML 3'b001 // complement
`define	lkLSB 3'b010 // AC bit 0
`define	lkMSB 3'b011 // AC bit 11
`define	lkCLL 3'b100 // set to zero
`define	lkSTL 3'b101 // set to one
`define	lkRTF 3'b110 // restore (RTF instruction)

// per OP Gr2
`define	 INV 3
`define	 SMA 6
`define	 SZA 5
`define	 SNL 4

// per IOT (IOP_req)
`define	 IOP1o  4'b1001
`define	 IOP2o  4'b1010
`define	 IOP4o  4'b1100
`define	 IOP1i  4'b0001
`define	 IOP2i  4'b0010
`define	 IOP4i  4'b0100
`define	 IOPNOP 4'b0000

`define	TSF 3'b001	// 6041 Skip if teleprinter flag is 1
`define	TCF 3'b010	// 6042 Clear teleprinter flag.
`define	TPC 3'b100	// 6044 Load the TTO from the content of AC 4-11 and print and/or punch the character
`define TLS 3'b110  // 6046 Load the TTO from the content of AC 4-11, clear the teleprinter flag, and print and/or punch the character.

`define	KSF 3'b001	// 6031 Skip if keyboard flag is a 1
`define	KCC 3'b010	// 6032 Clear AC and clear keyboard flag
`define	KRS 3'b100	// 6034 Read keyboard buffer static (This is a static command in that neither the AC nor the keyboard flag is cleared)
`define	KRB 3'b110  // 6036 Clear AC, clear keyboard flag, and read the content of the keyboard buffer into the content of AC


// id microciclo

`define 	uOP_NOID 4'b0000	// operazione generica
`define 	uOP_FET3 4'b0001	// FETCH3 - indica la uistr 3 del fetch; usato da int e swreg
`define 	uOP_INDR 4'b0010	// indirizzamento indiretto
`define 	uOP_DIR  4'b0011	// indirizzamento diretto, fino a prova contraria
`define 	uOP_LIF  4'b0100	// load IF da IB
`define 	uOP_LSF  4'b0101	// load Save Fields da IF e DF
`define 	uOP_CIDF 4'b0110	// clear IF and DF

`define 	uOP_FILLER 5'd0		// filler bir non usati uOP

// IOT boards identifier

`define 	bdIOT       0	    // IOT processor instructions module
`define 	bdTTY       1	    // console board (teleprinter and keyboard)
`define 	bdMEMX      2	    // memory extender
